Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 475

LPC Interface Bridge Registers (D31:F0)
Table 13-2. DMA Registers (Sheet 2 of 2)
Port
CEh
D0h
D4h
D6h
D8h
DAh
DCh
DEh
13.2.1 DMABASE_CA—DMA Base and Current Address Registers
I/O Address:
Default Value:
Lockable:
Bit
15:0
Datasheet
Alias
CFh
Channel 7 DMA Base & Current Count
Channel 4–7 DMA Command
D1h
Channel 4–7 DMA Status
D5h
Channel 4–7 DMA Write Single Mask
D7h
Channel 4–7 DMA Channel Mode
D9h
Channel 4–7 DMA Clear Byte Pointer
DBh
Channel 4–7 DMA Master Clear
DDh
Channel 4–7 DMA Clear Mask
DFh
Channel 4–7 DMA Write All Mask
Ch. #0 = 00h; Ch. #1 = 02h
Ch. #2 = 04h; Ch. #3 = 06h
Ch. #5 = C4h Ch. #6 = C8h
Ch. #7 = CCh;
Undefined
No
Base and Current Address — R/W. This register determines the address for the
transfers to be performed. The address specified points to two separate registers. On
writes, the value is stored in the Base Address register and copied to the Current
Address register. On reads, the value is returned from the Current Address register.
The address increments/decrements in the Current Address register after each transfer,
depending on the mode of the transfer. If the channel is in auto-initialize mode, the
Current Address register will be reloaded from the Base Address register after a
terminal count is generated.
For transfers to/from a 16-bit slave (channels 5–7), the address is shifted left one bit
location. Bit 15 will be shifted into Bit 16.
The register is accessed in 8 bit quantities. The byte is pointed to by the current byte
pointer flip/flop. Before accessing an address register, the byte pointer flip/flop should
be cleared to ensure that the low byte is accessed first.
Register Name
Attribute:
Size:
Power Well: Core
Description
Default Type
Undefined R/W
Undefined WO
Undefined RO
000001XXb WO
000000XXb WO
Undefined WO
Undefined WO
Undefined WO
0Fh R/W
R/W
16 bit (per channel),
but accessed in two 8-bit
quantities
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