Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 762

19.1.5 RID—Revision Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Offset Address: 08h
Default Value:
Bit
Revision ID — RO. See the Intel
7:0
of the RID Register.
19.1.6 PI—Programming Interface Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 09h
Default Value:
Bit
7:0
19.1.7 SCC—Sub Class Code Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 0Ah
Default Value:
Bit
7:0
19.1.8 BCC—Base Class Code Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 0Bh
Default Value:
Bit
7:0
762
See bit description
00h
Programming Interface — RO.
00h = No specific register level programming interface defined.
04h
Sub Class Code (SCC) — RO. This field is determined by bit 2 of the MPC register
(D28:F0-5:Offset D8h, bit 2).
04h = PCI-to-PCI bridge.
00h = Host Bridge.
06h
Base Class Code (BCC) — RO.
06h = Indicates the device is a bridge device.
PCI Express* Configuration Registers
Attribute:
Size:
Description
®
6 Series Chipset Specification Update for the value
Attribute:
Size:
Description
Attribute:
Size:
Description
Attribute:
Size:
Description
RO
8 bits
RO
8 bits
RO
8 bits
RO
8 bits
Datasheet