Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 852

22.1.21 PID—PCI Power Management Capability ID
Address Offset: 50h
Default Value:
Bit
15:8
7:0
22.1.22 PC—Power Management Capabilities
Address Offset: 52h
Default Value:
Bit
15:11
10
9
8:6
5
4
3
2:0
852
51h
–
0001h
Next Capability (NEXT) — RO. Indicates that this is the last capability structure in
the list.
Cap ID (CAP) — RO. Indicates that this pointer is a PCI power management capability
53h
–
0023h
PME_Support — RO. Indicates PME# is not supported
D2_Support — RO. The D2 state is not supported.
D1_Support — RO. The D1 state is not supported.
Aux_Current — RO. PME# from D3COLD state is not supported, therefore this field is
000b.
Device Specific Initialization (DSI) — RO. Indicates that device-specific
initialization is required.
Reserved
PME Clock (PMEC) — RO. Does not apply. Hardwired to 0.
Version (VS) — RO. Indicates support for Revision 1.2 of the PCI Power Management
Specification.
Thermal Sensor Registers (D31:F6)
Attribute: RO
Size: 16 bits
Description
Attribute: RO
Size: 16 bits
Description
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