Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 575

SATA Controller Registers (D31:F2)
14.1.40 ATS—APM Trapping Status Register (SATA–D31:F2)
Address Offset: C4h
Default Value:
Function Level Reset:No
.
Bit
7:4 Reserved
Secondary Slave Trap (SST) — R/WC. Indicates that a trap occurred to the
3
secondary slave device.
Secondary Master Trap (SPT) — R/WC. Indicates that a trap occurred to the
2
secondary master device.
Primary Slave Trap (PST) — R/WC. Indicates that a trap occurred to the primary
1
slave device.
Primary Master Trap (PMT) — R/WC. Indicates that a trap occurred to the primary
0
master device.
14.1.41 SP Scratch Pad Register (SATA–D31:F2)
Address Offset: D0h
Default Value:
.
Bit
Data (DT) — R/W. This is a read/write register that is available for software to use. No
31:0
hardware action is taken on this register.
Datasheet
00h
00000000h
Attribute: R/WC
Size: 8 bits
Description
Attribute: R/W
Size: 32 bits
Description
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