Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 403

Chipset Configuration Registers
10.1.73 BUC—Backed Up Control Register
Offset Address: 3414–3414h
Default Value:
All bits in this register are in the RTC well and only cleared by RTCRST#.
Bit
7:6
5
4
3:1
0
10.1.74 FD—Function Disable Register
Offset Address: 3418–341Bh
Default Value:
When disabling a function, only the configuration space is disabled. Software must
ensure that all functionality within a controller that is not desired (such as memory
spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function.
When a function is disabled, software must not attempt to re-enable it. A disabled
function can only be re-enabled by a platform reset.
Bit
31:26
25
24
23
Datasheet
0000000xb
Reserved
LAN Disable — R/W.
0 = LAN is Enabled
1 = LAN is Disabled.
This bit is locked by the Function Disable SUS Well Lockdown register. Once locked,
this bit can not be changed by software.
Daylight Savings Override (SDO) — R/W.
0 = Daylight Savings is Enabled.
1 = The DSE bit in RTC Register B is set to Read-only with a value of 0 to disable
daylight savings.
Reserved
Top Swap (TS) — R/W.
0 = PCH will not invert A16.
1 = PCH will invert A16 for cycles going to the BIOS space (but not the feature
space) in the FWH.
If PCH is strapped for Top-Swap (GNT3# is low at rising edge of PWROK), then this
bit cannot be cleared by software. The strap jumper should be removed and the
system rebooted.
See bit description
Reserved
Serial ATA Disable 2 (SAD2) — R/W. Default is 0.
0 = The SATA controller #2 (D31:F5) is enabled.
1 = The SATA controller #2 (D31:F5) is disabled.
Thermal Throttle Disable (TTD) — R/W. Default is 0.
0 = Thermal Throttle is enabled.
1 = Thermal Throttle is disabled.
PCI Express* 8 Disable (PE8D) — R/W. Default is 0. When disabled, the link for
this port is put into the "link down" state.
0 = PCI Express* port #8 is enabled.
1 = PCI Express port #8 is disabled.
Attribute: R/W
Size: 8-bit
Description
Attribute: R/W
Size: 32-bit
Description
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