Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 838

21.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Bit
31:29 Reserved
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 0 Limit.
28:16
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG0.Region Limit.
15:13 Reserved
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 0 Base
12:0
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG0.Region Base.
21.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Bit
31:29 Reserved
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 1 Limit.
28:16
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Limit.
15:13 Reserved
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 1 Base
12:0
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Base.
21.4.9 FREG2—Flash Region 2 (Intel
(GbE LAN Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Bit
31:29 Reserved
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 2 Limit.
28:16
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Limit.
15:13 Reserved
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 2 Base
12:0
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Base.
838
MBARB + 54h
00000000h
Description
MBARB + 58h
00000000h
Description
MBARB + 5Ch
00000000h
Description
Serial Peripheral Interface (SPI)
Attribute: RO
Size: 32 bits
Attribute: RO
Size: 32 bits
®
ME) Register
Attribute: RO
Size: 32 bits
Datasheet