Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 83

Signal Description
Table 2-24. General Purpose I/O Signals (Sheet 4 of 4)
Name Type Tolerance
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO[7:6]
GPIO[5:2] I/OD
GPIO1
GPIO0
NOTES:
1. All GPIOs can be configured as either input or output.
2. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to
either an SMI# or an SCI, but not both.
3. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO
signals are not driven high into powered-down planes. Also, external devices should not be
driving powered down GPIOs high. Some GPIOs may be connected to pins on devices that
exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core
power (PWROK low) or a Power Button Override event will result in the PCH driving a pin to
a logic 1 to another device that is powered down.
4. The functionality that is multiplexed with the GPIO may not be used in desktop
configuration.
5. When this signal is configured as GPO the output stage is an open drain.
6. In an Intel
7. GPIO18 will toggle at a frequency of approximately 1 Hz when the signal is programmed as
a GPIO (when configured as an output) by BIOS.
8. For GPIOs where GPIO vs. Native Mode is configured using SPI Soft Strap, the
corresponding GPIO_USE_SEL bits for these GPIOs have no effect. The GPIO_USE_SEL
bits for these GPIOs may change to reflect the Soft-Strap configuration even though GPIO
Lockdown Enable (GLE) bit is set.
9. These pins are used as Functional straps. See
10. Once Soft-strap is set to GPIO mode, this pin will default to GP Input. When Soft-strap is
SLP_LAN# usage and if Host BIOS does not configure as GP Output for SLP_LAN# control,
SLP_LAN# behavior will be based on the setting of the RTC backed SLP_LAN# Default Bit
(D31:F0:A4h:Bit 8).
11. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure
the signal is stable in its inactive state of the native functionality, immediately after reset
until it is initialized to GPIO functionality.
Datasheet
Power
Well
I/O 3.3 V Suspend
I/O 3.3 V Suspend
I/O 3.3 V Suspend
I/O 3.3 V Suspend
I/O 3.3 V Suspend
I/O 3.3 V Core
5 V Core
I/O 3.3 V Core
I/O 3.3 V Core
®
ME disabled system, GPIO31 may be used as ACPRESENT from the EC.
Blink
Default
Capability
Multiplexed with
LAN_PHY_PWR_CTRL. GPIO /
Native functionality controlled
Native Yes
using soft strap
(Note 8)
Multiplexed with SMBALERT#.
Native Yes
(Note 11)
Multiplexed with OC6#
Native Yes
(Note 11)
Multiplexed with OC5#
Native Yes
(Note 11)
GPO Yes Unmultiplexed
GPI Yes Mobile: Used as GPIO[7:6] only.
GPI Yes Multiplexed PIRQ[H:E]# (Note 5).
GPI Yes Mobile: Used as GPIO1 only.
GPI Yes Multiplexed with BMBUSY#
Section 2.27
Description
for more details.
83