Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 855

Thermal Sensor Registers (D31:F6)
22.2.1 TSIU—Thermal Sensor In Use
Offset Address:
Default Value:
Bit
7:1
0
22.2.2 TSE—Thermal Sensor Enable
Offset Address:
Default Value:
Bit
7:0
22.2.3 TSS—Thermal Sensor Status
Offset Address:
Default Value:
Bit
7
6
5
4
3
2:0
Datasheet
TBARB+00h
00h
Reserved.
Thermal Sensor In Use (TSIU) — R/W. This is a SW semaphore bit.
After a core well reset, a read to this bit returns a 0. After the first read, subsequent
reads will return a 1.
A write of a 1 to this bit will reset the next read value to 0. Writing a 0 to this bit has
no effect.
Software can poll this bit until it reads a 0, and will then own the usage of the thermal
sensor. This bit has no other effect on the hardware, and is only used as a semaphore
among various independent software threads that may need to use the thermal
sensor. Software that reads this register but does not intend to claim exclusive access
of the thermal sensor must write a 1 to this bit if it reads a 0, in order to allow other
software threads to claim it.
TBARB+01h
00h
Thermal Sensor Enable (TSE) — R/W. BIOS programs this register to enable the
thermal sensor.
TBARB+02h
00h
Catastrophic Trip Indicator (CTI) — RO.
0 = The temperature is below the catastrophic setting.
1 = The temperature is above the catastrophic setting.
Hot Trip Indicator (HTI) — RO.
0 = The temperature is below the Hot setting.
1 = The temperature is above the Hot setting.
Auxiliary Trip Indicator (ATI) — RO.
0 = The temperature is below the Auxiliary setting.
1 = The temperature is above the Auxiliary setting.
Reserved
Auxiliary2 Trip Indicator (ATI) — RO.
0 = The temperature is below the Auxiliary2 setting.
1 = The temperature is above the Auxiliary2 setting.
Reserved
Attribute: RO, R/W
Size: 8 bit
Description
Attribute: R/W
Size: 8 bit
Description
Attribute: RO
Size: 8 bit
Description
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