Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 444

12.1.25 MADDL—Message Address Low Register
(Gigabit LAN—D25:F0)
Address Offset: D4h–D7h
Default Value:
Bit
Message Address Low (MADDL) — R/W. Written by the system to indicate the lower
31:0 32 bits of the address to use for the MSI memory write transaction. The lower two bits
will always return 0 regardless of the write operation.
12.1.26 MADDH—Message Address High Register
(Gigabit LAN—D25:F0)
Address Offset: D8h–DBh
Default Value:
Bit
Message Address High (MADDH) — R/W. Written by the system to indicate the
31:0
upper 32 bits of the address to use for the MSI memory write transaction.
12.1.27 MDAT—Message Data Register
(Gigabit LAN—D25:F0)
Address Offset: DCh–DDh
Default Value:
Bit
Message Data (MDAT) — R/W. Written by the system to indicate the lower 16 bits of
31:0 the data written in the MSI memory write DWORD transaction. The upper 16 bits of the
transaction are written as 0000h.
12.1.28 FLRCAP—Function Level Reset Capability
(Gigabit LAN—D25:F0)
Address Offset: E0h–E1h
Default Value:
Bit
Next Pointer — RO. This field provides an offset to the next capability item in the
15:8
capability list. The value of 00h indicates the last item in the list.
Capability ID — RO. The value of this field depends on the FLRCSSEL bit.
7:0 13h = If FLRCSSEL = 0
09h = If FLRCSSEL = 1, indicating vendor specific capability.
444
See bit description
See bit description
See bit description
0009h
Gigabit LAN Configuration Registers
Attribute: R/W
Size: 32 bits
Description
Attribute: R/W
Size: 32 bits
Description
Attribute: R/W
Size: 16 bits
Description
Attribute: RO
Size: 16 bits
Description
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