Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 627

SATA Controller Registers (D31:F5)
15.1.24 PMCS—PCI Power Management Control and Status
Register (SATA–D31:F5)
Address Offset: 74h
Default Value:
Function Level Reset:No (Bits 8 and 15 only)
Bits
PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if
this bit and PMEE is set, a PME# will be generated from the SATA controller.
NOTE: When SCC=01h this bit will be RO 0. Software is advised to clear PMEE together
15
This bit is not reset by Function Level Reset.
14:9 Reserved
PME Enable (PMEE) — R/W. When SCC is not 01h, this bit R/W. When set, the SATA
controller generates PME# form D3
8 Note: When SCC=01h this bit will be RO 0. Software is advised to clear PMEE together
with PMES prior to changing SCC through MAP.SMS.
This bit is not reset by Function Level Reset.
7:4 Reserved
No Soft Reset (NSFRST) — RO. These bits are used to indicate whether devices
transitioning from D3
0 = Device transitioning from D3
1 = Device transitioning from D3
Configuration content is preserved. Upon transition from the D3
3
initialized state, no additional operating system intervention is required to preserve
configuration context beyond writing to the PowerState bits.
Regardless of this bit, the controller transition from D3
or bus segment reset will return to the state D0 uninitialized with only PME context
preserved if PME is supported and enabled.
2 Reserved
Power State (PS) — R/W. These bits are used both to determine the current power
state of the
SATA controller and to set a new power state.
00 = D0 state
1:0
11 = D3
When in the D3
and memory spaces are not. Additionally, interrupts are blocked.
Datasheet
75h
–
0008h
with PMES prior to changing SCC through MAP.SMS.
state to D0 state will perform an internal reset.
HOT
HOT
HOT
state
HOT
state, the controller's configuration space is available, but the I/O
HOT
Attribute:
Size:
Description
on a wake event.
HOT
state to D0 state perform an internal reset.
state to D0 state do not perform an internal reset.
state to D0 state by a system
HOT
RO, R/W, R/WC
16 bits
state to D0 state
HOT
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