Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 884

23.2.15 H_GS—Host General Status
(MEI—D22:F1)
Address Offset: 4Ch–4Fh
Default Value:
Bit
Host General Status(H_GS)— RO. General Status of Host, this field is not used by
31:0
Hardware
23.2.16 PID—PCI Power Management Capability ID Register
(MEI—D22:F1)
Address Offset: 50h–51h
Default Value:
Bit
15:8 Next Capability (NEXT) — RO. Value of 60h indicates the location of the next pointer.
Capability ID (CID) — RO. Indicates the linked list item is a PCI Power Management
7:0
Register.
23.2.17 PC—PCI Power Management Capabilities Register
(MEI—D22:F1)
Address Offset: 52h
Default Value:
Bit
PME_Support (PSUP) — RO. This five-bit field indicates the power states in which the
15:11 function may assert PME#. Intel MEI can assert PME# from any D-state except D1 or
D2 which are not supported by Intel MEI.
10:9 Reserved
Aux_Current (AC) — RO. Reports the maximum Suspend well current required when
8:6
in the D3
Device Specific Initialization (DSI) — RO. Indicates whether device-specific
5
initialization is required.
4 Reserved
3 PME Clock (PMEC) — RO. Indicates that PCI clock is not required to generate PME#.
Version (VS) — RO. Hardwired to 011b to indicate support for Revision 1.2 of the PCI
2:0
Power Management Specification.
884
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
00000000h
6001h
53h
–
C803h
state. Value of 00b is reported.
cold
Attribute: RO
Size: 32 bits
Description
Attribute: RO
Size: 16 bits
Description
Attribute: RO
Size: 16 bits
Description
Datasheet