Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 821

Serial Peripheral Interface (SPI)
21.1.17 PR4—Protected Range 4 Register
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Note: This register can not be written when the FLOCKDN bit is set to 1.
Bit
Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that writes and erases directed to addresses between
31
them (inclusive) must be blocked by hardware. The base and limit fields are ignored
when this bit is cleared.
30:29 Reserved
Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
28:16
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Read Protection Enable — R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
15
(inclusive) must be blocked by hardware. The base and limit fields are ignored when this
bit is cleared.
14:13 Reserved
Protected Range Base — R/W. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
12:0
000h for the base comparison. Any address less than the value programmed in this field
is unaffected by this protected range.
Datasheet
SPIBAR + 84h
00000000h
Description
Attribute: R/W
Size: 32 bits
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