Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 372

10.1.21 LSTS—Link Status Register
Offset Address: 21AA–21ABh
Default Value:
Bit
15:10
9:4
3:0
10.1.22 DMIC—DMI Control Register
Offset Address: 2234–2237h
Default Value:
Bit
31:2
1:0
10.1.23 CIR30—Chipset Initialization Register 30
Offset Address: 2238–223Bh
Default Value:
Bit
31:0
10.1.24 CIR5—Chipset Initialization Register 5
Offset Address: 228C– 228Fh
Default Value:
Bit
31:0
372
0042h
Reserved
Negotiated Link Width (NLW) — RO. Negotiated link width is x4 (000100b).
Current Link Speed (LS) — RO.
0001b = 2.5 Gb/s
0010b = 5.0 Gb/s
00000000h
Reserved
DMI Clock Gate Enable (DMICGEN) — R/W. BIOS must program this field to
11b.
00000000h
CIR30 Field 1 — R/W. BIOS must program this field to 00000001h.
00000000h
CIR5 Field 1 — R/W. BIOS must program this field to 00000001h.
Chipset Configuration Registers
Attribute: RO
Size: 16-bit
Description
Attribute: R/W
Size: 32-bit
Description
Attribute: R/W
Size: 32-bit
Description
Attribute: R/W
Size: 32-bit
Description
Datasheet