Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 368

10.1.11 V0CTL—Virtual Channel 0 Resource Control Register
Offset Address: 2014–2017h
Default Value:
Bit
31
30:27
26:24
23:16
15:10
9:7
6:1
0
10.1.12 V0STS—Virtual Channel 0 Resource Status Register
Offset Address: 201A–201Bh
Default Value:
Bit
15:2
1
0
368
80000011h
Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and
cannot be disabled.
Reserved
Virtual Channel Identifier (ID) — RO. Indicates the ID to use for this virtual
channel.
Reserved
Extended TC/VC Map (ETVM)— R/WL. Defines the upper 8-bits of the VC0 16-bit
TC/VC mapping registers. These registers use the PCI Express reserved TC[3] traffic
class bit. These bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set.
Reserved
Transaction Class / Virtual Channel Map (TVM) — R/WL. Indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel. These bits are locked if the
TCLOCKDN bit (RCBA+0050h:bit 31) is set.
Reserved
0000h
Reserved
VC Negotiation Pending (NP) — RO. When set, this bit indicates the virtual
channel is still being negotiated with ingress ports.
Reserved
Chipset Configuration Registers
Attribute: R/WL, RO
Size: 32-bit
Description
Attribute: RO
Size: 16-bit
Description
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