Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 768

19.1.21 INTR—Interrupt Information Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 3Ch–3Dh
Default Value:
Function Level Reset: No (Bits 7:0 only)
Bit
Interrupt Pin (IPIN) — RO. Indicates the interrupt pin driven by the root port. At
reset, this register takes on the following values that reflect the reset state of the
D28IP register in chipset config space:
15:8
NOTE: The value that is programmed into D28IP is always reflected in this register.
Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate
7:0 which interrupt line (vector) the interrupt is connected to. No hardware action is taken
on this register. These bits are not reset by FLR.
768
See bit description
Port Reset Value
1 D28IP.P1IP
2 D28IP.P2IP
3 D28IP.P3IP
4 D28IP.P4IP
5 D28IP.P5IP
6 D28IP.P6IP
7 D28IP.P7IP
8 D28IP.P8IP
PCI Express* Configuration Registers
Attribute: R/W, RO
Size: 16 bits
Description
Datasheet