Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 861

Thermal Sensor Registers (D31:F6)
22.2.12 AE—Alert Enable
Offset Address: TBARB+3Fh
Default Value:
Bit
7
6:5
4
3
2:0
22.2.13 PTL— Processor Temperature Limit
Offset Address: TBARB+56h
Default Value:
Bit
15:0
22.2.14 PTV — Processor Temperature Value
Offset Address: TBARB+60h
Default Value:
Bit
15:8
7:0
Datasheet
00h
Lock Enable — R/W.
0 = Lock Disabled.
1 = Lock Enabled. This will lock this register (including this bit)
This bit is reset by a Host Partitioned Reset. Note that CF9 warm reset is a Host
Partitioned Reset.
Reserved
PCH Alert Enable — R/W.
When this bit is set, it will assert the PCH's TEMP_ALERT# pin if the PCH temperature
is outside the temperature limits.
This bit is lockable by bit 7 in this register.
DIMM Alert Enable — R/W.
When this bit is set, it will assert the PCH's TEMP_ALERT# pin if DIMM1-4 temperature
is outside of the temperature limits.
Note that the actual DIMMs that are read and used for the alert are enabled in the TRC
register (offset 1Ah).
This bit is lockable by bit 7 in this register.
NOTE: Same Upper and Lower limits for triggering TEMP_ALERT# are used for all
enabled DIMMs in the system.
Reserved.
0000h
Processor Temperature Limit — R/W. These bits are programmed by BIOS.
0000h
Reserved.
Processor Temperature Value— RO. These bits contain the processor package
temperature
Attribute: R/W
Size: 8 bit
Description
Attribute: R/W
Size: 16 bit
Description
Attribute: RO
Size: 16 bit
Description
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