Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 424

11.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 28h–2Bh
Default Value:
Bit
Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the
31:0
prefetchable address base.
11.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 2C–2Fh
Default Value:
Bit
Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the
31:0
prefetchable address limit.
11.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0)
Offset Address: 34h
Default Value:
Bit
Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
7:0
capabilities list is at 50h in configuration space.
11.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0)
Offset Address: 3Ch
Default Value:
Bit
15:8 Interrupt Pin (IPIN) — RO. The PCI bridge does not assert an interrupt.
Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this register.
7:0
Since the bridge does not generate an interrupt, BIOS should program this value to FFh
as per the PCI bridge specification.
424
00000000h
00000000h
50h
3Dh
–
0000h
PCI-to-PCI Bridge Registers (D30:F0)
Attribute: R/W
Size: 32 bits
Description
Attribute: R/W
Size: 32 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: R/W, RO
Size: 16 bits
Description
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