Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 744

18.1.13 SID—Subsystem Identification Register
(SMBus—D31:F2/F4)
Address Offset: 2Eh
Default Value:
Lockable:
Bit
Subsystem ID (SID) — R/WO. The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems from each other. The
value returned by reads to this register is the same as that which was written by BIOS
15:0
into the IDE SID register.
NOTE: Software can write to this register only once per core well reset. Writes should
18.1.14 INT_LN—Interrupt Line Register (SMBus—D31:F3)
Address Offset: 3Ch
Default Value:
Bit
Interrupt Line (INT_LN) — R/W. This data is not used by the PCH. It is to
7:0 communicate to software the interrupt line that the interrupt pin is connected to
PIRQB#.
18.1.15 INT_PN—Interrupt Pin Register (SMBus—D31:F3)
Address Offset: 3Dh
Default Value:
Bit
Interrupt PIN (INT_PN) — RO. This reflects the value of D31IP.SMIP in chipset
7:0
configuration space.
744
2Fh
–
0000h
No
be done as a single 16-bit cycle.
00h
See description
SMBus Controller Registers (D31:F3)
Attribute: R/WO
Size: 16 bits
Power Well: Core
Description
Attributes: R/W
Size: 8 bits
Description
Attributes: RO
Size: 8 bits
Description
Datasheet