Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 438

12.1.10 MBARA—Memory Base Address Register A
(Gigabit LAN—D25:F0)
Address Offset: 10h
Default Value:
The internal CSR registers and memories are accessed as direct memory mapped
offsets from the base address register. SW may only access whole DWord at a time.
Bit
31:17
16:4
3
2:1
0
12.1.11 MBARB—Memory Base Address Register B
(Gigabit LAN—D25:F0)
Address Offset: 14h
Default Value:
The internal registers that are used to access the LAN Space in the External FLASH
device. Access to these registers are direct memory mapped offsets from the base
address register. Software may only access a DWord at a time.
Bit
31:12
11:4
3
2:1
0
438
13h
–
00000000h
Base Address (BA) — R/W. Software programs this field with the base address of
this region.
Memory Size (MSIZE) — R/W. Memory size is 128 KB.
Prefetchable Memory (PM) — RO. The GbE LAN controller does not implement
prefetchable memory.
Memory Type (MT) — RO. Set to 00b indicating a 32 bit BAR.
Memory / IO Space (MIOS) — RO. Set to 0 indicating a Memory Space BAR.
17h
–
00000000h
Base Address (BA) — R/W. Software programs this field with the base address of
this region.
Memory Size (MSIZE) — R/W. Memory size is 4 KB.
Prefetchable Memory (PM) — RO. The Gb LAN controller does not implement
prefetchable memory.
Memory Type (MT) — RO. Set to 00b indicating a 32 bit BAR.
Memory / IO Space (MIOS) — RO. Set to 0 indicating a Memory Space BAR.
Gigabit LAN Configuration Registers
Attribute: R/W, RO
Size: 32 bits
Description
Attribute: R/W, RO
Size: 32 bits
Description
Datasheet