Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 648

16.1.16 INT_PN—Interrupt Pin Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 3Dh
Default Value:
Bit
Interrupt Pin — RO. This reflects the value of D29IP.E1IP (Chipset Config
Registers:Offset 3108:bits 3:0) or D26IP.E2IP (Chipset Config Registers:Offset
7:0
3114:bits 3:0).
NOTE: Bits 7:4 are always 0h
16.1.17 PWR_CAPID—PCI Power Management Capability ID
Register (USB EHCI—D29:F0, D26:F0)
Address Offset: 50h
Default Value:
Bit
Power Management Capability ID — RO. A value of 01h indicates that this is a PCI
7:0
Power Management capabilities field.
16.1.18 NXT_PTR1—Next Item Pointer #1 Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 51h
Default Value:
Bit
Next Item Pointer 1 Value — R/W (special). This register defaults to 58h that
indicates that the next capability registers begin at configuration offset 58h. This
register is writable when the WRT_RDONLY bit (D29:F0, D26:F0:80h, bit 0) is set. This
allows BIOS to effectively hide the Debug Port capability registers, if necessary. This
7:0 register should only be written during system initialization before the plug-and-play
software has enabled any master-initiated traffic. Only values of 58h (Debug Port and
FLR capabilities visible) and 98h (Debug Port invisible, next capability is FLR) are
expected to be programmed in this register.
NOTE: Register not reset by D3-to-D0 warm reset.
648
See Description
01h
58h
EHCI Controller Registers (D29:F0, D26:F0)
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
Datasheet