Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 561

SATA Controller Registers (D31:F2)
14.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2)
Address Offset: 3Ch
Default Value:
Function Level Reset:No
Bit
Interrupt Line — R/W. This field is used to communicate to software the interrupt line
that the interrupt pin is connected to.
7:0
Interrupt Line register is not reset by FLR.
14.1.21 INT_PN—Interrupt Pin Register (SATA–D31:F2)
Address Offset: 3Dh
Default Value:
Bit
7:0
14.1.22 IDE_TIM — IDE Timing Register (SATA–D31:F2)
Address Offset: Primary:
Default Value:
Bit
15
14:0
14.1.23 PID—PCI Power Management Capability Identification
Register (SATA–D31:F2)
Address Offset: 70h
Default Value:
Bits
Next Capability (NEXT) — RO.
15:8 B0h — if SCC = 01h (IDE mode) indicating next item is FLR capability pointer.
A8h — for all other values of SCC to point to the next capability structure.
Capability ID (CID) — RO. Hardwired to 01h. Indicates that this pointer is a PCI power
7:0
management.
Datasheet
00h
See Register Description
Interrupt Pin — RO. This reflects the value of D31IP.SIP (Chipset Config
Registers:Offset 3100h:bits 11:8).
40h
Secondary: 42h
0000h
IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or
Secondary decode.
0 = Disable.
1 = Enables the PCH to decode the associated Command Blocks (1F0–1F7h for primary,
170–177h for secondary, or their native mode BAR equivalents) and Control Block
(3F6h for primary, 376h for secondary, or their native mode BAR equivalents).
This bit effects the IDE decode ranges for both legacy and native-mode decoding.
Reserved
71h
–
See Register Description
Attribute:
Size:
Description
Attribute:
Size:
Description
41h Attribute:
–
43h
–
Size:
Description
Attribute:
Size:
Description
R/W
8 bits
RO
8 bits
R/W
16 bits
RO
16 bits
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