1Apm Power Management (Desktop Only); 2Mobile Apm Power Management (Mobile Only); 13Reset Behavior - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

However, the operating system is assumed to be at least APM enabled. Without APM
calls, there is no quick way to know when the system is idle between keystrokes. The
PCH does not support burst modes.
5.13.12.1 APM Power Management (Desktop Only)
The PCH has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and
Enable register, generates an SMI once per minute. The SMI handler can check for
system activity by reading the DEVTRAP_STS register. If none of the system bits are
set, the SMI handler can increment a software counter. When the counter reaches a
sufficient number of consecutive minutes with no activity, the SMI handler can then put
the system into a lower power state.
If there is activity, various bits in the DEVTRAP_STS register will be set. Software clears
the bits by writing a 1 to the bit position.
The DEVTRAP_STS register allows for monitoring various internal devices, or Super I/O
devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions
on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts.
5.13.12.2 Mobile APM Power Management (Mobile Only)
In mobile systems, there are additional requirements associated with device power
management. To handle this, the PCH has specific SMI traps available. The following
algorithm is used:
1. The periodic SMI timer checks if a device is idle for the require time. If so, it puts
the device into a low-power state and sets the associated SMI trap.
2. When software (not the SMI handler) attempts to access the device, a trap occurs
(the cycle doesn't really go to the device and an SMI is generated).
3. The SMI handler turns on the device and turns off the trap.
4. The SMI handler exits with an I/O restart. This allows the original software to
continue.
5.13.13 Reset Behavior
When a reset is triggered, the PCH will send a warning message to the processor to
allow the processor to attempt to complete any outstanding memory cycles and put
memory into a safe state before the platform is reset. When the processor is ready, it
will send an acknowledge message to the PCH. Once the message is received the PCH
asserts PLTRST#.
The PCH does not require an acknowledge message from the processor to trigger
PLTRST#. A global reset will occur after 4 seconds if an acknowledge from the
processor is not received.
When the PCH causes a reset by asserting PLTRST# its output signals will go to their
reset states as defined in
A reset in which the host platform is reset and PLTRST# is asserted is called a Host
Reset or Host Partition Reset. Depending on the trigger a host reset may also result in
power cycling see
out before receiving an acknowledge message from the processor a Global Reset with
power cycle will occur. A reset in which the host and ME partitions of the platform are
reset is called a Global Reset.
Table 5-39
180
Chapter
Table 5-39 for details. If a host reset is triggered and the PCH times
shows the various reset triggers.
3.
Functional Description
Datasheet