Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 462

13.1.25 GEN3_DEC—LPC I/F Generic Decode Range 3 Register
(LPC I/F—D31:F0)
Offset Address: 8Ch
Default Value:
Bit
31:24
23:18
17:16
15:2
1
0
462
8Eh
–
00000000h
Reserved
Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position
indicates that any value in the corresponding address bit in a received cycle will be
treated as a match. The corresponding bit in the Address field, below, is ignored. The
mask is only provided for the lower 6 bits of the DWord address, allowing for decoding
blocks up to 256 bytes in size.
Reserved
Generic I/O Decode Range 3 Base Address (GEN3_BASE) — R/W.
NOTE: The PCH Does not provide decode down to the word or byte level
Reserved
Generic Decode Range 3 Enable (GEN3_EN) — R/W.
0 = Disable.
1 = Enable the GEN3 I/O range to be forwarded to the LPC I/F
LPC Interface Bridge Registers (D31:F0)
Attribute: R/W
Size: 32 bit
Power Well: Core
Description
Datasheet