Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 812

Bit
Block/Sector Erase Size (BERASE) — RO. This field identifies the erasable sector
size for all Flash components.
Valid Bit Settings:
00 = 256 Byte
01 = 4 K Byte
10 = 8 K Byte
4:3
11 = 64 K Byte
If the FLA is less than FPBA, then this field reflects the value in the LVSCC.LBES
register.
If the FLA is greater or equal to FPBA, then this field reflects the value in the
UVSCC.UBES register.
NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing
made to access the BIOS region using the direct access method or an access to the
BIOS Program Registers that violated the security restrictions. This bit is simply a log of
2
an access security violation. This bit is cleared by software writing a 1.
NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing
Flash Cycle Error (FCERR) — R/W/C. Hardware sets this bit to 1 when an program
register access is blocked to the FLASH due to one of the protection policies or when
any of the programmed cycle registers is written while a programmed access is already
in progress. This bit remains asserted until cleared by software writing a 1 or until
1 hardware reset occurs due to a global reset or host partition reset in an Intel
enabled system. Software must clear this bit before setting the FLASH Cycle GO bit in
this register.
NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing
Flash Cycle Done (FDONE) — R/W/C. The PCH sets this bit to 1 when the SPI Cycle
completes after software previously set the FGO bit. This bit remains asserted until
cleared by software writing a 1 or hardware reset due to a global reset or host partition
reset in an Intel
0 is set, an internal signal is asserted to the SMI# generation block. Software must make
sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed
access.
NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing
812
is being used.
Access Error Log (AEL) — R/W/C. Hardware sets this bit to a 1 when an attempt was
is being used.
is being used.
®
ME enabled system. When this bit is set and the SPI SMI# Enable bit
is being used.
Serial Peripheral Interface (SPI)
Description
®
ME
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