Intel 82562EZ Design Manual
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Intel 82562EZ Design Manual

Intel 82562EZ Design Manual

Dual footprint
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82540EP/82541(PI/GI/EI) &
82562EZ(EX) Dual Footprint
Design Guide
Application Note
Networking Silicon
317506-001
Revision 2.9

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Summary of Contents for Intel 82562EZ

  • Page 1 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Application Note Networking Silicon 317506-001 Revision 2.9...
  • Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
  • Page 3 Updated reference schematics to reflect current differential pair termination resistor values for the 82541(PI/GI/EI) and 82540EP. Updated section 4.2.1 “Termination Resistors for Designs Based on 82562EZ/EX PLC Device” to reflect current resistor and RBIAS values. Updated section 4.3.1 “Termination Resistors for Designs Based on 82541xx” to reflect current resistor values.
  • Page 4 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Note: This page is intentionally left blank.

  • Page 5: Table Of Contents

    Reference Documents...................2 Product Codes....................... 2 System Data Port Interfaces.................... 3 LCI Connection to 82562EZ(EX) Platform LAN Connect Device ......3 PCI Interface for 82540EP/82541xx Family of Gigabit Controllers ....... 4 Ethernet Component Design Guidelines ...............5 General Design Considerations for Ethernet Controllers ........5 3.1.1...
  • Page 6 4.2.1 Termination Resistors for Designs Based on 82562EZ(EX) PLC ..30 4.2.2 Light Emitting Diodes for Designs Based on 82562EZ(EX) PLC ... 31 Layout for the 82541xx Gigabit Ethernet Controller ..........31 4.3.1 Termination Resistors for Designs Based on 82541xx ......31 4.3.2...
  • Page 7 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Tables LAN Component Connections/Features..............1 Product Ordering Codes..................2 Crystal Parameters....................5 82541PI Recommended Crystals................6 82562EZ(EX) Memory Layout (128 Byte EEPROM)...........12 82562EZ(EX) Memory Layout (512 Byte EEPROM)...........12 82562EZ(EX) Recommended Magnetics Modules ..........12 Microwire 64 x 16 Serial EEPROMs..............15...
  • Page 8 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Note: This page intentionally left blank. viii...

  • Page 9: Introduction

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Introduction Intel currently supports several footprint compatible Ethernet options depending upon the target application. The term “footprint compatible” means that the silicon devices are all manufactured in a 15 mm x 15 mm, 196-ball grid array package with the same ball pattern. Many of the critical signal pin locations are identical, allowing designers to create a single LAN on Motherboard (LOM) design that accommodates all devices.

  • Page 10: Reference Documents

    • 82541 Family of Gigabit Ethernet Controllers Datasheet. Intel Corporation. • I/O Control Hub 2, 3, and 4 EEPROM Map and Programming Information. Intel Corporation. • I/O Control Hub 5, 6, and 7 EEPROM Map and Programming Information. Intel Corporation.

  • Page 11: System Data Port Interfaces

    Line termination mechanisms are not specified for the LCI. Slew rate controlled output buffers achieve acceptable signal integrity by controlling signal reflection, undershoot and ringing. For details about how to connect the LCI interface between the 82562EZ(EX) Platform LAN Connect device and ICH5, please refer to the 82562ET/EM Platform LAN Connect Printed Circuit ®...

  • Page 12: Pci Interface For 82540Ep/82541Xx Family Of Gigabit Controllers

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide PCI Interface for 82540EP/82541xx Family of Gigabit Controllers The 82540EP and 82541xx controllers provide 32-bit interfaces for a 33 MHz or 66 MHz PCI bus meeting PCI 2.3 Specifications. The PCI 2.3 Specification trace routing instructions should be followed.

  • Page 13: Ethernet Component Design Guidelines

    Ethernet Component Design Guidelines This section provides recommendations for selecting components and connecting special pins. The main design elements are the 82562EZ(EX) Platform LAN Connect device or the 82540EP/ 82541xx Gigabit Ethernet Controller, a magnetics module with RJ-45 connector, and a crystal clock source.

  • Page 14: 82541Pi Recommended Crystals

    3.1.1.2 Nominal Frequency Intel® Ethernet controllers use a crystal frequency of 25.000 MHz. The 25 MHz input is used to generate a 125 MHz transmit clock for 100BASE-TX and 1000BASE-TX operation; 10 MHz and 20 MHz transmit clocks, for 10BASE-T operation.

  • Page 15: Crystal Circuit

    Figure 2 illustrates a simplified schematic of the 82562EZ(EX) and the 82540EP/82541xx controller’s crystal circuit. The crystal and the capacitors form a feedback element for the internal inverting amplifier. This combination is called parallel-resonant, because it has positive reactance at the selected frequency.
  • Page 16 The formula for crystal load capacitance is as follows: ⋅ C1 C2 ------------------------- stray where C1 = C2 = 22 pF (as suggested in most Intel reference designs) and C = allowance for additional capacitance in pads, traces and the chip carrier stray within the Ethernet controller package An allowance of 3 pF to 7 pF accounts for lumped stray capacitance.

  • Page 17: Reference Crystal

    CLoad capacitance. Note: For the 82541EI/GI devices, Intel® recommends choosing a crystal with a ESR value of 20 Ω or less, an equivalent Cload of 18 pF, and a maximum of 30 ppm frequency shift. Cload is defined to be the load capacitance of the crystal, specified by the crystal vendor.

  • Page 18: Circuit Board

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide 3.1.4 Circuit Board Since the dielectric layers of the circuit board are allowed some reasonable variation in thickness, the stray capacitance from the printed board (to the crystal circuit) will also vary. If the thickness tolerance for the outer layers of dielectric are controlled within ±17 percent of nominal, then the...

  • Page 19: Designing With The 82562Ez(Ex) Platform Lan Connect Device

    Isolate Mode. 3.2.2 Serial EEPROM for 82562EZ(EX) Implementations Serial EEPROM for LAN implementations based on 82562EZ(EX) devices connects to the ICH5. Depending upon the size of the EEPROM, the 82562EZ(EX) may or may not support legacy manageability. Table 5 Table 6 list the EEPROM map for the 82562EZ(EX) PLC device.

  • Page 20: Magnetics Modules For 82562Ez(Ex) Plc Device

    3.2.4 Power Supplies for 82562EZ(EX) PLC Implementations The 82562EZ(EX) PLC device uses a single 3.3 V power supply. The 3.3 V supply must provide approximately 90 mA current for full speed operation. Standby power must be furnished in order to wake up from powerdown.

  • Page 21: Designing With The 82541Xx Gigabit Controllers

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Designing with the 82541xx Gigabit Controllers This section provides design guidelines specific to the 82541xx Gigabit Ethernet Controllers. 3.3.1 82541xx Ethernet Controller LAN Disable Guidelines The 82541xx controller has a LAN disable function that is present on FLSH_SO, ball P9. This pin...

  • Page 22: Serial Eeprom For 82541Xx Controller Implementations

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Note: To use this configuration for the 82562EZ(EX) Platform LAN Connect device, be sure the AND gate U1 is populated. Depopulate the 0 Ω resistor R2. 82562EZ(EX) Disable Circuit Super IO Chip Control...

  • Page 23: Eeprom Map Information

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide The EEPROM access algorithm programmed into the 82541xx controller is compatible with most, but not all, commercially available 3.3 V Microwire* interface, serial EEPROM devices, with 64 x 16 (or 256 x 16) organization and a 1 MHz speed rating. The 82541xx EEPROM access algorithm drives extra pulses on the shift clock at the beginnings and ends of read and write cycles.

  • Page 24: Magnetics Modules For 82541Xx Controller Applications

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide 3.3.4 Magnetics Modules for 82541xx Controller Applications There are several different types of magnetics modules. For example, some magnetics modules have USB connectors or RJ-45 connectors. There are also several discrete modules that can be used for optimal performance.
  • Page 25 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide 3.3.5.1 82541GI (B1 Stepping) Oscillator Solution C4=1uF VDD=3.3 VDD=3.3 R1=200K C1=10pF oscillator Cstray R2=30K 82541GI Tabor VDD=3.3 B1 step R3=3K R4=1K C3=1uF The oscillator solution for the 82541GI includes capacitor C1, which forms a capacitor divider with capacitor C of approximately 20 pF.
  • Page 26 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide 3.3.5.2 82541PI (C0 Stepping) Oscillator Solution There are two oscillator solutions for the 82541PI: high voltage and low voltage. High Voltage Solution (VDD = 3.3 V) This solution involves capacitor C1, which forms a capacitor divider with C of about 20 pF.

  • Page 27: Power Supplies For The 82541Xx Controller

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide 3.3.6 Power Supplies for the 82541xx Controller The 82541xx controller requires three power supplies: 1.2 V, 1.8 V, and 3.3 V. The 1.2 V supply must provide approximately 500 mA current, and the 1.8 V supply, approximately 230 mA current.

  • Page 28: 82541Xx Device Test Capability

    A Boundary Scan Definition Language (BSDL) file describing the 82541xx device is available for use in your test environment. The controller also contains an XOR test tree mechanism for simple board tests. Details of XOR tree operation may be obtained through your Intel representative.

  • Page 29: Ethernet Component Layout Guidelines

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Ethernet Component Layout Guidelines These sections provide recommendations for performing printed circuit board layouts. Good layout practices are essential to meet IEEE PHY conformance specifications and EMI regulatory requirements. General Layout Considerations for Ethernet Controllers Critical signal traces should be kept as short as possible to decrease the likelihood of being affected by high frequency noise from other signals, including noise carried on power and ground planes.

  • Page 30: Crystals

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Integrated RJ-45 Keep silicon traces at least 1 inch from edge of PCB (2 inches preferred) w/LAN Magnetics Keep LAN silicon 1 to 4 inches from LAN connector Keep 100 mil minimum distance between TX...

  • Page 31: Board Stackup Recommendations

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide 4.1.3 Board Stackup Recommendations Printed Circuit Boards (PCBs) for these designs typically have four, six, eight, or more layers. Following is a description of a typical four-layer board stackup: • Layer 1 is a signal layer. It can contain the differential analog pairs from the Ethernet device to the magnetics module.

  • Page 32: Signal Trace Geometry

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide 45° 45° Figure 6. Trace Routing • Traces should be routed away from board edges by a distance greater than the trace height above the ground plane. This allows the field around the trace to couple more easily to the ground plane rather than to adjacent wires or boards.

  • Page 33: Trace Length And Symmetry

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide When performing a board layout, do not allow the CAD tool auto-router to route the differential pairs without intervention. In most cases, the differential pairs will have to be routed manually. The components should be laid out in the following order of priority: 1.

  • Page 34: Signal Isolation

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide 4.1.9 Signal Isolation To maintain best signal integrity, keep digital signals far away from the analog traces. A good rule of thumb is no digital signal should be within 300 mils (7.5 mm) of the differential pairs. If digital signals on other board layers cannot be separated by a ground plane, they should be routed at right angles with respect to the differential pairs.

  • Page 35: Traces For Decoupling Capacitors

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide 4.1.11 Traces for Decoupling Capacitors Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long and thin traces are more inductive and would reduce the intended effect of decoupling capacitors.

  • Page 36: Ideal Ground Split Implementation

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Board Edge RJ/Mag. Chassis RJ Shield Capacitor Capacitor connected to Stuffing Stuffing Chassis Options Options Digital Resistive Terminations Figure 8. Ideal Ground Split Implementation...

  • Page 37: Non-Integrated Magnetics Modules And Rj-45 Connectors

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide The following table lists the reference starting values for these capacitors. Capacitors Value 4.7µF or 10 µF C3, C4 470 pF to 0.1 µF C1, C2, C5, C6 The placement of C1 through C6 may also be different for each board design (in other words, not all of the capacitors may need to be populated).

  • Page 38: Layout For The 82562Ez(Ex) Plc Device

    Additional capacitance that may be required for EFT testing LAN_term_plane Figure 9. Termination Plane Example for 82562EZ(EX) PLC Device and Discrete Magnetics Layout for the 82562EZ(EX) PLC Device This section provides layout guidelines specific to the 82562EZ(EX) PLC device. 4.2.1 Termination Resistors for Designs Based on 82562EZ(EX) PLC Two differential pairs are terminated using 54.9 Ω...

  • Page 39: Light Emitting Diodes For Designs Based On 82562Ez(Ex) Plc

    Light Emitting Diodes for Designs Based on 82562EZ(EX) PLC The 82562EZ(EX) PLC device has three high-current outputs to directly drive LEDs for link, activity and speed indication. Since LEDs are likely to be integral to a magnetics module, take care to route the LED traces away from potential sources of EMI noise.

  • Page 40: Troubleshooting Common Physical Layout Issues

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Crucial tests are as follows, listed in priority order: 1. Bit Error Rate (BER). This test is a good indicator of real world network performance. It should be done with long and short cables and many link partners. The test limit is 10 to 11 errors (10/100/1000 Mbps).
  • Page 41 5 Ω to 20 Ω. Short traces will have fewer problems if the differential impedance is slightly off target. 9. For 82562EZ(EX) PLC designs, use of capacitor that is too large between the transmit traces or too much capacitance on the magnetics module’s transmit center tap to ground. Using capacitors more than a few picoFarads in either of these locations can slow the 100 Mbps rise and fall time.
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  • Page 43: Design And Layout Checklists

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Design and Layout Checklists The Design and Layout Checklists are in Portable Data Format (PDF) and available to aid designers via http://developer.intel.com. at: http://www.intel.com/design/network/products/lan/docs/82541pi_docs.htm...
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  • Page 45: Ball Number To Signal Mapping With Population Options

    The signal names may vary slightly from the names in Section 7.0 since the names used in the reference schematics follow conventions used by Intel design engineers on their design tools. Table 13. Ball Number to Signal Mapping (Sheet 1 of 8) Population Options...
  • Page 46 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Table 13. Ball Number to Signal Mapping (Sheet 2 of 8) (Continued) Population Options 82541xx Ball 82540EP 82562EZ 82541xx 82540EP 82562EZ Comments Pin Name Pin Name Name LED3/LINK1000# LINK1000# TOUT No stuff Testability output for 82562EZ(EX).
  • Page 47 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Table 13. Ball Number to Signal Mapping (Sheet 3 of 8) (Continued) Population Options 82541xx Ball 82540EP 82562EZ 82541xx 82540EP 82562EZ Comments Pin Name Pin Name Name CLKR_1.8V ISOL_TI 1.8V 2.5 V No stuff...
  • Page 48 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Table 13. Ball Number to Signal Mapping (Sheet 4 of 8) (Continued) Population Options 82541xx Ball 82540EP 82562EZ 82541xx 82540EP 82562EZ Comments Pin Name Pin Name Name MDI[2]+ MDI[2]+ Magnetics Magnetics Magnetics 10/100...
  • Page 49 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Table 13. Ball Number to Signal Mapping (Sheet 5 of 8) (Continued) Population Options 82541xx Ball 82540EP 82562EZ 82541xx 82540EP 82562EZ Comments Pin Name Pin Name Name HSDACN MDI[3]+ MDI[3]+ Magnetics Magnetics Magnetics...
  • Page 50 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Table 13. Ball Number to Signal Mapping (Sheet 6 of 8) (Continued) Population Options 82541xx Ball 82540EP 82562EZ 82541xx 82540EP 82562EZ Comments Pin Name Pin Name Name 1.2 V 1.5 V 1.2 V 1.5 V...
  • Page 51 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Table 13. Ball Number to Signal Mapping (Sheet 7 of 8) (Continued) Population Options 82541xx Ball 82540EP 82562EZ 82541xx 82540EP 82562EZ Comments Pin Name Pin Name Name EESK EESK EESK EESK EESK If EE from ICH...
  • Page 52 This column will be checked if the 82562EZ pin names are different from their 82540EP/82541xx counterparts. This column will be checked if the 82562EZ signal is different from the 82540EP/82541xx AND the 82562EZ gets a connection.

  • Page 53: Dual Footprint Reference Schematic

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Dual Footprint Reference Schematic The following pages illustrate a dual purpose 10/100 Mbps and 10/100/1000 Mbps design using the 82562EZ(EX) Platform LAN Connect device and the 82540EP/82541xx Gigabit Ethernet Controller.
  • Page 54 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide...
  • Page 55 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide...
  • Page 56 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide...
  • Page 57 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide...
  • Page 58 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide...
  • Page 59 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide...
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  • Page 61: Measuring Lan Reference Frequency Using A Frequency Counter

    ±50 parts per million (ppm). Note: Intel recommends a frequency tolerance of ±30 (ppm). Most Intel LAN devices will operate properly with a 25.000 MHz reference crystal, provided it meets the recommended requirements for frequency stability, equivalent series resistance at resonance (ESR), and load capacitance.

  • Page 62: Indirect Probing Method

    Almost all Intel LAN silicon that support 1000BASE-T Ethernet can provide a buffered 125 MHz clock, which can be used for indirect probing of the transmitter reference clock. The buffered 125 MHz clock will be a 5X multiple of the crystal circuit’s reference frequency...

  • Page 63: Indirect Frequency Measurement And Frequency Accuracy Calculation Steps

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Indirect Frequency Measurement and Frequency Accuracy Calculation Steps 1. Make sure the system BIOS has the LAN controller enabled. 2. Connect the test equipment as shown in Figure 3. Using the appropriate controls for your model of high resolution digital counter, make sure it can display ~125.0000 MHz with at least four decimal places frequency resolution.

  • Page 64: Direct Probing Test Method, Applicable For Most 10/100 Devices

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Example 2. Given: The measured averaged center frequency is 125.00087 MHz (or 125,000,870 Hertz). 125000870 125000000 – FrequencyAccuracy ppm ---------------------------------------------------------------- 6.96ppm ⁄ 125000000 1000000 Note: The following items should be noted for an ideal reference crystal on a typical printed circuit board.

  • Page 65: Direct Frequency Measurement And Frequency Accuracy Calculation Steps

    82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Figure 12. Direct Probing Method Direct Frequency Measurement and Frequency Accuracy Calculation Steps 1. Make sure the system BIOS has the LAN controller enabled. 2. Connect the test equipment as shown in Figure 3.
  • Page 66 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide – FrequencyAccuracy ppm ------------------------------- - ⁄ y 1000000 where x = Average measured frequency in Hertz and y = Ideal reference frequency in Hertz Example 3. Given: The measured averaged center frequency is 24.99963 MHz (or 24,999,630 Hertz).

  • Page 67: B Gigconf.exe Register Settings For 82541Gi(Ei) Devices

    1. Boot to DOS using a DOS Boot Diskette. 2. Launch Gigconf from the diskette (gigconf.exe). 3. Select the Intel network connection to be measured. a. If multiple adapters are installed, use the arrow keys to navigate to highlight the selected adapter and press Enter.
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