Bus Master Ide I/O Register Address Map - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

SATA Controller Registers (D31:F2)
14.2 Bus Master IDE I/O Registers (D31:F2)
The bus master IDE function uses 16 bytes of I/O space, allocated using the BAR
register, located in Device 31:Function 2 Configuration space, offset 20h. All bus
master IDE I/O space registers can be accessed as byte, word, or DWord quantities.
Reading reserved bits returns an indeterminate, inconsistent value, and writes to
reserved bits have no affect (but should not be attempted). These registers are only
used for legacy operation. Software must not use these registers when running AHCI.
All I/O registers are reset by Function Level Reset. The register address I/O map is
shown in
Table 14-2. Bus Master IDE I/O Register Address Map
BAR+
Offset
00
01
02
03
04–07
08
09
0Ah
0Bh
0Ch–
0Fh
10h
14h
Datasheet
Table 14-2.
Mnemonic
BMICP Command Register Primary
— Reserved
BMISP Bus Master IDE Status Register Primary
— Reserved
Bus Master IDE Descriptor Table Pointer
BMIDP
Primary
BMICS Command Register Secondary
— Reserved
BMISS Bus Master IDE Status Register Secondary
— Reserved
Bus Master IDE Descriptor Table Pointer
BMIDS
Secondary
AIR AHCI Index Register
AIDR AHCI Index Data Register
Register Default Type
00h R/W
— RO
R/W, R/WC,
00h
RO
— RO
xxxxxxxxh R/W
00h R/W
— RO
R/W, R/WC,
00h
RO
— RO
xxxxxxxxh R/W
00000000h R/W, RO
xxxxxxxxh R/W
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