Mei Mmio Register Address Map (Ve - D23:F0) - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

23.2.26 HERX—MEI Extend Register DWX
(MEI—D22:F1)
Address Offset: HER1: C0h–C3h
Default Value:
Bit
Extend Register DWX (ERDWX):
Xth DWORD result of the extend operation.
31:0
NOTE: Extend Operation is HER[5:1] if using SHA-1. If using SHA-2, then Extend
23.3 MEI0_MBAR—MEI0 MMIO Registers
These MMIO registers are accessible starting at the MEI MMIO Base Address
(MEI_MBAR) which gets programmed into D22:F0:Offset 10–17h. These registers are
reset by PLTRST# unless otherwise noted.
Table 23-2. MEI MMIO Register Address Map (VE — D23:F0)
MEI_MBAR+Of
fset
00–03h
04h–07h
08h–0Bh
0Ch–0Fh
23.3.1 H_CB_WW—Host Circular Buffer Write Window
(MEI MMIO Register)
Address Offset: MEI0_MBAR + 00h
Default Value:
Bit
Host Circular Buffer Write Window Field (H_CB_WWF). This bit field is for host to
write into its circular buffer. The host's circular buffer is located at the ME subsystem
address specified in the Host CB Base Address register. This field is write only, reads will
31:0
return arbitrary data. Writes to this register will increment the H_CBWP as long as
ME_RDY is 1. When ME_RDY is 0, writes to this register have no effect and are not
delivered to the H_CB, nor is H_CBWP incriminated.
888
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
HER2: C4h–C7h
HER3: C8h–CBh
HER4: CCh–CFh
HER5: D0h–D3h
HER6: D4h–D7h
HER7: D8h–DBh
HER8: DCh–DFh
00000000h
Operation is HER[8:1].
Mnemonic Register Name
H_CB_WW Host Circular Buffer Write Window
H_CSR Host Control Status
ME_CB_RW ME Circular Buffer Read Window
ME CSR_HA ME Control Status Host Access
00000000h
Attribute: RO
Size: 32 bits
Description
Default
00000000h
02000000h
00000000h
02000000h
Attribute: RO
Size: 32 bits
Description
Type
RO
R/W, R/WC,
RO
RO
RO
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