Region Access Control Table - Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet

3. The component section has information about the SPI flash in the system including:
the number of components, density of each, illegal instructions (such as chip
erase), and frequencies for read, fast read and write/erase instructions.
4. The Region section points to the three other regions as well as the size of each
region.
5. The master region contains the security settings for the flash, granting read/write
permissions for each region and identifying each master by a requestor ID. See
Section 5.24.2.1
6 & 7. The processor and PCH soft strap sections contain processor and PCH
configurable parameters.
8. The Reserved region between the top of the processor strap section and the bottom
of the OEM Section is reserved for future chipset usages.
9. The Descriptor Upper MAP determines the length and base address of the
Management Engine VSCC Table.
10. The Management Engine VSCC Table holds the JEDEC ID and the VSCC information
of the entire SPI Flash supported by the NVM image.
11. OEM Section is 256 Bytes reserved at the top of the Flash Descriptor for use by
OEM.
5.24.2.1 Descriptor Master Region
The master region defines read and write access setting for each region of the SPI
device. The master region recognizes three masters: BIOS, Gigabit Ethernet, and
Management Engine. Each master is only allowed to do direct reads of its primary
regions.
Table 5-56. Region Access Control Table
Region
Descriptor
BIOS
Management
Engine
Gigabit Ethernet
Platform Data
Region
246
for more information.
Master Read/Write Access
Processor and BIOS
N/A
Processor and BIOS
can always read from
and write to BIOS
Region
Read / Write
Read / Write
N/A
ME
N/A
Read / Write
®
Intel ME can always
read from and write to
Intel ME Region
Read / Write always read from and
N/A
Functional Description
GbE Controller
N/A
Read / Write
Read / Write
GbE software can
write to GbE region
N/A
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