Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 552

Table 14-1. SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 2 of 2)
Offset
42h–43h
70h–71h
72h–73h
74h–75h
80h–81h
82h–83h
84h–87h
88h–89h
90h
92h–93h
94h–97h
9Ch–9Fh
A0h
A4h
A8h–ABh
ACh–AFh
B0h–B1h
B2h–B3h
B4h–B5h
C0h
C4h
D0h–D3h
E0h–E3h
E4h–E7h
E8h–EBh
NOTE: The PCH SATA controller is not arbitrated as a PCI device; therefore, it does not need a
master latency timer.
552
Mnemonic Register Name
IDE_TIM Secondary IDE Timing Register
PID PCI Power Management Capability ID
PC PCI Power Management Capabilities
PCI Power Management Control and
PMCS
Status
Message Signaled Interrupt Capability
MSICI
ID
Message Signaled Interrupt Message
MSIMC
Control
Message Signaled Interrupt Message
MSIMA
Address
Message Signaled Interrupt Message
MSIMD
Data
MAP Address Map
PCS Port Control and Status
SCGC SATA Clock Gating Control
SCLKGC SATA Clock General Configuration
SIRI SATA Indexed Registers Index
STRD SATA Indexed Register Data
SATACR0 SATA Capability Register 0
SATACR1 SATA Capability Register 1
FLRCID FLR Capability ID
FLRCLV FLR Capability Length and Version
FLRCTRL FLR Control
ATC APM Trapping Control
ATS ATM Trapping Status
SP Scratch Pad
BFCS BIST FIS Control/Status
BFTD1 BIST FIS Transmit Data, DW1
BFTD2 BIST FIS Transmit Data, DW2
SATA Controller Registers (D31:F2)
Default Type
0000h
See register
description
See register
description
See register R/W, RO,
description R/WC
7005h
0000h RO, R/W
00000000h RO, R/W
0000h
0000h
0000h R/W, RO
00000000h
00000000h R/W, R/WO
00h
XXXXXXXXh
0010B012h RO, R/WO
00000048h
0009h
See register
R/WO, RO
description
0000h RO, R/W
00h
00h R/WC
00000000h
00000000h R/W, R/WC
00000000h
00000000h
Datasheet
R/W
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
RO
RO
R/W
R/W
R/W
R/W