Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 837

Serial Peripheral Interface (SPI)
21.4.6 FRAP—Flash Regions Access Permissions Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Bit
31:28 Reserved
GbE Master Write Access Grant (GMWAG) — R/W. Each bit 27:25 corresponds to
Master[3:1]. GbE can grant one or more masters write access to the GbE region 3
overriding the permissions in the Flash Descriptor.
27:25
Master[1] is Host Processor/BIOS, Master[2] is Intel
is Host processor/GbE.
The contents of this register are locked by the FLOCKDN bit.
24:20 Reserved
GbE Master Read Access Grant (GMRAG) — R/W. Each bit 19:17 corresponds to
Master[3:1]. GbE can grant one or more masters read access to the GbE region 3
overriding the read permissions in the Flash Descriptor.
19:17
Master[1] is Host processor/BIOS, Master[2] is Intel
is GbE.
The contents of this register are locked by the FLOCKDN bit
16:12 Reserved
GbE Region Write Access (GRWA) — RO. Each bit 11:8 corresponds to Regions 3:0.
If the bit is set, this master can erase and write that particular region through register
accesses.
11:8
The contents of this register are that of the Flash Descriptor. Flash Master 3.Master
Region Write Access OR a particular master has granted GbE write permissions in their
Master Write Access Grant register OR the Flash Descriptor Security Override strap is
set.
7:4 Reserved
GbE Region Read Access (GRRA) — RO. Each bit 3:0 corresponds to Regions 3:0. If
the bit is set, this master can read that particular region through register accesses.
3:0
The contents of this register are that of the Flash Descriptor. Flash Master 3.Master
Region Write Access OR a particular master has granted GbE read permissions in their
Master Read Access Grant register.
Datasheet
MBARB + 50h
00000808h
Description
Attribute: RO, R/W
Size: 32 bits
®
Management Engine, Master[3]
®
Management Engine, Master[3]
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