Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 363

Chipset Configuration Registers
10.1.2 RPC—Root Port Configuration Register
Offset Address: 0400–0403h
Default Value:
Bit
31:12
11
10:8
7:4
3:2
1:0
Datasheet
0000000yh (y = 00xxb)
Reserved
GbE Over PCIe Root Port Enable (GBEPCIERPEN) — R/W.
0 = GbE MAC/PHY communication is not enabled over PCI Express.
1 = The PCI Express port selected by the GBEPCIEPORTSEL register will be used for
GbE MAC/PHY over PCI Express communication
The default value for this register is set by the GBE_PCIE_EN soft strap.
Note: GbE and PCIe will use the output of this register and not the soft strap
GbE Over PCIe Root Port Select (GBEPCIERPSEL) — R/W. If the GBEPCIERPEN
is a '1', then this register determines which port is used for GbE MAC/PHY
communication over PCI Express. This register is set by soft strap and is writable to
support separate PHY on motherboard and docking station.
111 = Port 8 (Lane 7)
110 = Port 7 (Lane 6)
101 = Port 6 (Lane 5)
100 = Port 5 (Lane 4)
101 = Port 4 (Lane 3)
010 = Port 3 (Lane 2)
001 = Port 2 (Lane 1)
000 = Port 1 (Lane 0)
The default value for this register is set by the GBE_PCIEPORTSEL[2:0] soft strap.
Note: GbE and PCIe will use the output of this register and not the soft strap
Reserved
Port Configuration2 (PC2) — RO. This controls how the PCI bridges are organized
in various modes of operation for Ports 5–8. For the following mappings, if a port is
not shown, it is considered a x1 port with no connection.
This bit is set by the PCIEPCS2[1:0] soft strap.
11 = 1 x4, Port 5 (x4)
10 = 2 x2, Port 5 (x2), Port 7 (x2)
01 = 1x2 and 2x1s, Port 5 (x2), Port 7 (x1) and Port 8(x1)
00 = 4 x1s, Port 5 (x1), Port 6 (x1), Port 7 (x1) and Port 8 (x1)
Port Configuration (PC) — RO. This controls how the PCI bridges are organized in
various modes of operation for Ports 1–4. For the following mappings, if a port is not
shown, it is considered a x1 port with no connection.
These bits are set by the PCIEPCS1[1:0] soft strap.
11 = 1 x4, Port 1 (x4)
10 = 2 x2, Port 1 (x2), Port 3 (x2)
01 = 1x2 and 2x1s, Port 1 (x2), Port 3 (x1) and Port 4 (x1)
00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3 (x1) and Port 4 (x1)
Attribute: R/W, RO
Size: 32-bit
Description
363