Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 689

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Integrated Intel High Definition Audio Controller Registers
17.1.1.11 HEADTYP—Header Type Register
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(Intel
Address Offset: 0Eh
Default Value:
Bit
7:0 Header Type — RO. Hardwired to 00.
17.1.1.12 HDBARL—Intel
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(Intel
Address Offset: 10h–13h
Default Value:
Bit
Lower Base Address (LBA) — R/W. Base address for the Intel
31:14 controller's memory mapped configuration registers. 16 Kbytes are requested by
hardwiring bits 13:4 to 0s.
13:4 Reserved.
3 Prefetchable (PREF) — RO. Hardwired to 0 to indicate that this BAR is NOT prefetchable
Address Range (ADDRNG) — RO. Hardwired to 10b, indicating that this BAR can be
2:1
located anywhere in 64-bit address space.
Space Type (SPTYP) — RO. Hardwired to 0. Indicates this BAR is located in memory
0
space.
17.1.1.13 HDBARU—Intel
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(Intel
Address Offset: 14h–17h
Default Value:
Bit
Upper Base Address (UBA) — R/W. Upper 32 bits of the Base address for the Intel
31:0
High Definition Audio controller's memory mapped configuration registers.
Datasheet
High Definition Audio Controller—D27:F0)
00h
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High Definition Audio Lower Base Address Register
High Definition Audio—D27:F0)
00000004h
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High Definition Audio Upper Base Address Register
High Definition Audio Controller—D27:F0)
00000000h
Attribute: RO
Size: 8 bits
Description
Attribute: R/W, RO
Size: 32 bits
Description
Attribute: R/W
Size: 32 bits
Description
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High Definition Audio
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