Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 420

11.1.7 PMLT—Primary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address: 0Dh
Default Value:
Bit
Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base
7:3
Specification, Revision 1.0a.
2:0 Reserved
11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0)
Offset Address: 0Eh
Default Value:
Bit
7 Multi-Function Device (MFD) — RO. A 0 indicates a single function device
Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the
6:0
configuration space, which is a PCI-to-PCI bridge in this case.
11.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0)
Offset Address: 18h–1Ah
Default Value:
Bit
Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number
23:16
below the bridge.
15:8 Secondary Bus Number (SCBN) — R/W. Indicates the bus number of PCI.
Primary Bus Number (PBN) — R/W. This field is default to 00h. In a multiple-PCH
system, programmable PBN allows an PCH to be located on any bus. System
7:0
configuration software is responsible for initializing these registers to appropriate
values. PBN is not used by hardware in determining its bus number.
420
00h
01h
000000h
PCI-to-PCI Bridge Registers (D30:F0)
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: R/W
Size: 24 bits
Description
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