Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 805

High Precision Event Timer Registers
Bit
3
2
1
0
NOTE: Reads or writes to unimplemented timers should not be attempted. Read from any
unimplemented registers will return an undetermined value.
Datasheet
Timer n Type (TIMERn_TYPE_CNF) — R/W or RO.
Timer 0:Bit is read/write. 0 = Disable timer to generate periodic interrupt; 1 =
Enable timer to generate a periodic interrupt.
Timers 1, 2, 3, 4, 5, 6, 7: Hardwired to 0. Writes have no affect.
Timer n Interrupt Enable (TIMERn_INT_ENB_CNF) — R/W. This bit must be set
to enable timer n to cause an interrupt when it times out.
0 = Disable (Default). The timer can still count and generate appropriate status bits,
but will not cause an interrupt.
1 = Enable.
Timer Interrupt Type (TIMERn_INT_TYPE_CNF) — R/W.
0 = The timer interrupt is edge triggered. This means that an edge-type interrupt is
generated. If another interrupt occurs, another edge will be generated.
1 = The timer interrupt is level triggered. This means that a level-triggered interrupt
is generated. The interrupt will be held active until it is cleared by writing to the
bit in the General Interrupt Status Register. If another interrupt occurs before the
interrupt is cleared, the interrupt will remain active.
Timer 4, 5, 6, 7: This bit is Read Only, and will return 0 when read
Reserved. These bits will return 0 when read.
Description
805