Intel Stratix 10 Mx Hbm2 Controller Features - Intel Stratix 10 MX HBM2 IP User Manual

Table of Contents

1 Introduction to High Bandwidth Memory

UG-20031 | December 2017

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DDR commands entered on each positive

commands require two memory cycles; all other command are single-cycle

commands.

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Supports command, write data and read data parity.

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Support for bank grouping.

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Support for data bus inversion.

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Data mask for masking write data per byte. (Not available with ECC.)

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I/O voltage of 1.2V and DRAM core voltage of 1.2V.

1.4 Intel Stratix 10 MX HBM2 Controller Features

Intel Stratix 10 MX FPGAs offer the following controller features.

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User applications communicate with the HBMC using the AXI4 Protocol.

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There is one AXI4 interface per HBM2 Pseudo Channel. Each HBM2 interface

supports a maximum of sixteen AXI4 interfaces to the sixteen Pseudo Channels.

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The full-rate user interface can operate at a frequency lower than the HBM2

interface frequency For information on supported clock frequencies, refer to Intel

Stratix 10 MX HBM2 Supported Frequencies in Intel Stratix 10 MX HBM2 IP

Controller Interface Signals.

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The controller offers 32B and 64B access granularity supporting burst length 4 (BL

4) and pseudo-BL 8 (two back to back BL4).

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The controller offers out-of-order command scheduling and read data reordering.

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The controller supports a user-initiated refresh command (enabled through the

side band Advanced Peripheral Bus (APB) interface).

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The controller supports data mask or error correction code (ECC). When you do

not use data mask or ECC, you may use those bits as additional data bits.