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Table 5-2.
Signal
ADRO* - ADRF*
ADRIO* - ADR13*
DATO* - DATF*
INH1*
INIT*
IOWC*
LOCK*
MRDC*
INTERFACING INFORMATION
MULTIBUS
connector Pl signal Descriptions
Functional Description
Address.
These 20 lines transmit the address
of the memory location or I/O port to be
accessed. ADR13 is the most significant
address bit.
Data. These 16 bidirectional data lines
transmit and receive data to and from the
addressed memory location or I/O port. DATF*
is the most significant bit.
Inhibit RAM. For system application, allows
the RAM addresses to be overlaid by another
RAM or ROM in the system.
Initialize.
This signal resets the entire
system to a known internal state. The
iSBC 546, iSBC 547 and iSBC 548 boards are
slave boards and will never generate INIT*.
These boards require an INIT* pulse of 50
microseconds or longer for proper operation.
I/O write. Indicates the address of an I/O
port is on the MULTI BUS interface address
lines and that the contents on the MULTIBUS
interface data lines are to be accepted by the
addressed port.
Lock. When the MULTIBUS master accesses the
on-board dual port RAM and activates LOCK*
the on-board resources are locked out by the
dual port RAM until the MULTI BUS master
removes LOCK*.
Memory Read Command.
Indicates that a memory
location address is on the MULTIBUS interface
address lines and that the contents of that
location are to be read on the MULTIBUS
interface data lines.
5-3
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