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Intel Manuals
Controller
iSBC 546
Hardware reference manual
Intel iSBC 546 Hardware Reference Manual
High performance terminal controllers
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Contents
Table of Contents
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Table of Contents
Chapter 1 General Information
Table of Contents
Introduction
Board Features
Board Description
Isbc 548 Board Description
Specifications
Chapter 2 Board Operation
Introduction
Isbc 547 and Isbc 548 Functional Descriptions
Isbc 546 Functional Description
Chapter 3 Installation
Introduction
Unpacking and Inspection
Compatible Equipment
Installation Considerations
Connector Configurations
Battery Backup
Cabling
Pin to Pin Wiring List
Installation Procedures
Chapter 4 Programmingconsiderations
Introduction
Jumpers
Addressing
Programming Considerations
Firmware
80186 Processor Programming Considerations
8255 Programming
DSR Port
Chapter 5 Interfacing Information
Introduction
Multibus Information
MULTI BUS Connector Pl Pin Assignments
MULTI BUS Connector Pl Signal Descriptions
Connector P2 Pin Assignments
Serial Interfaces
Serial Connectors Pin Assignments, Isbc 546
547 Board
Serial Connectors Pin Assignments, Isbc 548
548 Board
Printer Interface Connector J5 Pin Assignments
Chapter 6 Service Assistance Information
Introduction
Service and Repair Assistance
Service Diagrams
Appendix Ajumper Information
Introduction
Jumper Combinations Isbc 547/548 Boards
Flag Byte Address Jumpers
Flag Byte Address Options and Jumpers
MULTIBUS Interrupt Jumpers
Memory Mapping Jumpers
Memory Map Jumpers and Addresses
Isbc
Appendix Bfirmware
Introduction
Isbc 546, Isbc
Firmware Operation
Recommendations for High Performance
Functional Architecture
Structures of Dual Ported RAM
Static Structures
Dynamic Structures
Receive Buffers
Transmit Buffers
Layout of Shared (Dual Port) Memory
Test Engineering Boot Area Layout
Static Structure Area Layout
Dynamic Structure Layout
Layout of Queue Area
Inter-Processor Messages
B.3.2.L Host CPU to Controller Messages
Initialize
Conf Igure
Initialize Message Format
Enable Message F0Ril1At
Disable Message Format
Transmit Buffer
Transmit Buffer Message Format
Abort Transmit Message Format
Suspend Transmit
Suspend Transmit Message Format
Resume Transmit
Resume Transmit Message Format
Assert DTR Message Format
Set CTS and CD Gates Message Format
Clear CTS and CD Gates Message Format
Set DSR Report Message Format
Clear DSR Report Message Format
Set RI Report Message Format
Clear RI Report Message Format
Clear DTR Message Format
Set Break Message Format
Clear Break Message Format
Download Message Format
Execute Command Message Format
Clear Receive Buffer Command Message Format
Transmit Complete Message Format
Input Available Message Format
Download Complete Message Format
Carrier Detect Message Format
Carrier Loss Message Format
Initialization Responses Message Format
Autobaud Complete Message Format
Special Character Received Message Format
DSR Detected Message Format
DSR Lost Message Format
RI Detected Message Format
RI Lost Message Format
EPROM Checksum
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iSBC® 546/547/548
HIGH PERFORMANCE
TERMINAL CONTROLLERS
HARDWARE REFERENCE MANUAL
Order Number: 122704-001
Copyright 1986, Intel Corporation, All Rights Reserved
I
Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051
r
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Isbc 548
Isbc 547
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