Board Operation; Introduction; Isbc 547 And Isbc 548 Functional Descriptions - Intel iSBC 546 Hardware Reference Manual

2.1 INTRODUCTION
CHAPTER 2
BOARD OPERATION
This chapter describes the operation of the three controller
boards, the iSBC 546, the iSBC 547, and the iSBC 548. The iSBC 547
and iSBC 548 boards are functionally identical and their operation
will be described jointly. The iSBC 546 board will be considered
separately.
2.2
iSBC 547 AND iSBC 548 FUNCTIONAL DESCRIPTIONS
Figure 2-1 is a block diagram for the iSBC 547 and iSBC 548
boards. The boards are functionally identical and differ only in
dimensions and in the type and number of serial interface
connectors (eight 9-pin connectors for the iSBC 547 and two 40-pin
connectors for the iSBC 548).
The iSBC 547 and iSBC 548 boards can not address the MULTIBUS
interface, both are slave boards only. The interface to the
~ruLTIBUS is through edge connectors PI and P2.
30th boards use an Intel 80186 microprocessor, operating at 8 Mhz
as their main processors. The 80186 has a 16 bit data bus and 16
bit internal architecture. The 80186 provides all bus controls
without the need of a separate bus controller device.
'rhe 80186 on the iSBC 547/548 controls eight serial channels
sending data ,through them, from the MULTIBUS host or receiving
data, through them, to the
MUL'l~IBUS
host. Data transfer to and
from the MULTIBUS is by use of a 32K Byte communication table
(shared dual port memory) in the on-board dual-port RAM. The
HULTIBUS host informs the on-bc)ard 80186 which serial channels are
enabled. The 80186 then polls those channels continuously, looking
for data from the MULTIBUS host, or the need to supply data to the
HULTIBUS host.
The structure of the communication table is described in Appendix
B, section B.3.1 of this manual. The main blocks in the
communication table in the on-board RAM are: a command queue
(dynamic structures area), a status queue (static structures
2-1