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Chapter 21
Configuring Channelized STM1 Interfaces
Channelized STM1 Interfaces Overview
Configuring Channelized STM1 IQ and IQE Interfaces
Configuring an STM1 IQ or STM1 IQE Interface
Channelized STM1 Interfaces Overview on page 473
Configuring Channelized STM1 IQ and IQE Interfaces on page 473
Configuring Channelized STM1 Interfaces on page 479
Configuring Link PIC Failover on Channelized STM1 Interfaces on page 486
Example: Configuring Channelized STM1 Interfaces on page 487
Each Channelized STM1 PIC and Channelized STM1 Intelligent Queuing (IQ) PIC has
one STM1 port.
For the Channelized STM1 IQ or IQE PIC, you can channelize the single port to the
NxDS0 level. Each E1 interface has 32 time slots (DS0), in which time slot 0 is
reserved.
You can combine one or more of these DS0 time slots (channels) to create a channel
group (NxDS0).
This section includes the following topics:
Configuring an STM1 IQ or STM1 IQE Interface on page 473
Configuring E1 IQ and IQE Interfaces on page 474
Configuring Fractional E1 IQ and IQE Interfaces on page 475
Configuring an NxDS0 IQ Interface on page 476
Example: Configuring Channelized STM1 IQ and IQE Interfaces on page 477
On a one-port Channelized STM1 IQ PIC, or each individual port of the 4-port
Channelized STM1 IQE PIC, you can configure one SDH STM1 interface. To configure
an SDH STM1 interface, include the no-partition interface-type statement at the
[edit interfaces cstm1-fpc/pic/port]
[edit interfaces cstm1-fpc/pic/port]
hierarchy level, specifying the so interface type:
Channelized STM1 Interfaces Overview
473
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