Table 34: Frame Relay DLCI Limitations for Channelized Interfaces (continued)
PIC Types
E1 level channels (Channelized STM1 IQ or IQE PIC)
OC3 level channels (Channelized OC3 IQ or IQE, or Channelized
OC12 IQ or IQE PIC)
OC12 level channels (Channelized OC12 IQ or IQE, Channelized
OC48/STM16 IQE PICs, and (per port on) OC12 ports on
4xOC12/STM4 IQE PICs)
STM1 level channel (Channelized STM1 IQ or IQE PIC)
T1 level channels (Channelized DS3 IQ or IQE PIC)
T1 level channels (Channelized OC3 IQ or IQE, or Channelized
OC12 IQ or IQE PIC)
T3 level channel (Channelized DS3 IQ or IQE, Channelized OC3 IQ
or IQE, or Channelized OC12 IQ or IQE PIC)
Table 35: Per Unit Scheduler DLCI Limitations for Channelized Interfaces
PIC Types
DS0 level channels
T1/E1 level channels
DS3/E3 level channels
SONET
†
In these router, PIC, and scheduler configurations, combining multiple protocol families per PIC changes the number of
Frame Relay DLCIs as shown in Table 36 on page 397.
Table 36: Protocol Family Combinations
Protocol Family Combinations
inet
inet6
mpls
Number of DLCIs per Level
Non M40e Platforms
With
Without
Per-Unit-Scheduler
Per-Unit-Scheduler
64
64
64
64
†
975
Protocol family
combinations apply
†
975
Protocol family
combinations apply
Data-Link Connection Identifiers on Channelized Interfaces
Chapter 17: Channelized Interfaces
Number of DLCIs
per Level
Range
64
1–1022 (0 is reserved for the LMI)
1022
1–1022 (0 is reserved for the LMI)
1022
1–1022 (0 is reserved for the LMI)
1022
1–1022 (0 is reserved for the LMI)
64
1–1022 (0 is reserved for the LMI)
64
1–1022 (0 is reserved for the LMI)
1022
1–1022 (0 is reserved for the LMI)
M40e Platform Only
With
Per-Unit-Scheduler
16
64
256
975
Number of DLCIs per PIC
3600
3600
3000
Without
Per-Unit-Scheduler
16
64
256
†
Protocol family
combinations apply
397