Figure 27: Channelized Cstm1 Ports (In Sdh Mode) On Channelized; Figure 28: Channelized Stm1 Iq Pic - Juniper JUNOS 10.1 - CONFIGURATION GUIDE 1-2010 Configuration Manual

Figure 27: Channelized CSTM1 Ports (in SDH Mode) on Channelized OC3/STM1 IQE PIC
SDH transport layer:
-cstm1-fpc/pic/port
SDH path layer:
-cau4-fpc/pic/port
NxDS0:
-ds- fpc/pic/port
[1-63]:[1-31]

Figure 28: Channelized STM1 IQ PIC

SDH transport layer:
-cstm1-fpc/pic/port
SDH path layer:
-cau4-fpc/pic/port:
ITU-T mapped CE1: KLM mapped CE1:
-ce1-fpc/pic/port: -ct1-fpc/pic/port:
[1-63] [1-63]
NxDS0:
-ds-fpc/pic/port:
[1-63]:[1-31]
ITU-T mapped E1: KLM mapped E1:
-e1-fpc/pic/port: -e1-fpc/pic/port:
[1-63] [1-63]
HDLC
Structure of Channelized IQ and Channelized IQE PICs
Chapter 17: Channelized Interfaces
Clear-channel path
layer STM1:
-so- fpc/pic/port
HDLC
Clear-channel path layer STM1:
-so-fpc/pic/port
407