Figure 25: Channelized Oc12/Stm4 Iq Pic (In Sdh Mode); Figure 26: Channelized Oc3 Ports (In Sonet Mode) On Channelized Oc3 Iq - Juniper JUNOS 10.1 - CONFIGURATION GUIDE 1-2010 Configuration Manual

JUNOS 10.1 Network Interfaces Configuration Guide

Figure 25: Channelized OC12/STM4 IQ PIC (in SDH Mode)

SDH transport layer:
-cstm4-fpc/pic/port
SDH path layer:
-cau4-fpc/pic/port
[1:4]
CT3:
-ct3- fpc/pic/port:
[1-4]:[1-3]
CT1: T1:
-ct1- fpc/pic/port:
-t1- fpc/pic/port:
[1-4]:[1-3]:[1-28]
[1-4]:[1-3]:[1-28]
NxDS0:
-ds-fpc/pic/port:[1-4]:[1-3]:[1-28]:[1-24]
Figure 26: Channelized OC3 Ports (in SONET Mode) on Channelized OC3 IQ and Channelized OC3/STM1 IQE
PICs
SONET transport layer:
-coc3-fpc/pic/port
SONET path layer:
-coc1-fpc/pic/port: [1-3]
M13-mapped CT3:
-ct3-fpc/pic/port:[1-3]
M13-mapped CT1: M13-mapped T1:
ct1-fpc/pic/port: t1-fpc/pic/port:
[1-3]:[1-28] [1-3]:[1-28]
NxDS0:
-ds-fpc/pic/port:
[1-3]:[1-28]:[1-24]
406
Structure of Channelized IQ and Channelized IQE PICs
T3:
-t3- fpc/pic/port:
[1-4]:[1-3]
HDLC
VT-mapped CT1: VT-mapped T1:
ct1-fpc/pic/port: t1-fpc/pic/port:
[1-63]:[1-28] [1-3]:[1-28]
NxDS0:
-ds-fpc/pic/port:
[1-3]:[1-28]:[1-24]
STM1 and STM4:
-so-fpc/pic/port
Clear-channel
path layer STM1:
-so-fpc/pic/port
Clear-channel T3:
-t3-fpc/pic/port:[1-3]
HDLC