Configuring Channelized Oc3 Iq And Iqe Interfaces; Channelized Oc3 Iq And Iqe Overview; Partitions, Oc Slices, Interface Types, And Time Slots; Configuring A Clear Channel On Channelized Oc3 Iq And Iqe Pics - Juniper JUNOS 10.1 - CONFIGURATION GUIDE 1-2010 Configuration Manual

Chapter 20
Configuring Channelized OC3 IQ and IQE
Interfaces

Channelized OC3 IQ and IQE Overview

Channelized OC3 IQ and IQE Overview on page 463
Partitions, OC Slices, Interface Types, and Time Slots on page 464
Configuring a Clear Channel on Channelized OC3 IQ and IQE PICs on page 465
Configuring T3 Interfaces on IQ and IQE Interfaces on page 465
Configuring T1 and NxDS0 Interfaces on page 466
Configuring Fractional T1 IQ Interfaces on page 470
Configuring Link PIC Failover on Channelized OC3 IQ and IQE
Interfaces on page 470
Channelized intelligent queuing (IQ) and channelized enhanced intelligent queuing
(IQE) interfaces allow arbitrary and dynamic channelization of serial links, allowing
greater flexibility than regular channelized interfaces.
On each port of a Channelized OC3 IQ or a Channelized OC3 IQE interface, you can
configure the following interface types:
One OC3 SONET interface
Up to three T3 interfaces
Up to 84 T1 interfaces
Up to three E3 interfaces (COC3 IQE PICs in SDH mode)
Up to 63 E1 interfaces (COC3 IQE PICs in SDH mode)
Up to 336 NxDS0 interfaces on an M Series router
Up to 768 NxDS0 interfaces on a T Series router
Figure 45 on page 464 shows an example of how a Channelized OC3 PIC might be
partitioned. In the figure, the OC3 SONET interface would be a standalone interface
because it would use the entire bandwidth of the PIC. The same applies to each port
of the 2–port Channelized OC3 Enhanced IQ (IQE) PIC.
Channelized OC3 IQ and IQE Overview
463