JUNOS 10.1 Network Interfaces Configuration Guide
on page 410 through Table 40 on page 412 show the structure of channelized IQE PICs,
channelized IQ PICs, and channelized PICs.
Figure 21: Channelized OC48/STM16 IQE PIC (in SONET Mode)
SONET transport layer:
-coc48-fpc/pic/port
SONET path layer:
-coc1-fpc/pic/port: [1-48]
M13-mapped CT3:
-ct3-fpc/pic/port:[1-48]
M13-mapped CT1:
M13-mapped T1:
-ct1-fpc/pic/port:
-t1-fpc/pic/port:
[1-48]:[1-28]
[1-48]:[1-28]
NxDS0:
-ds-fpc/pic/port:
[1-48]:[1-28]:[1-24]
Figure 22: Channelized OC48/STM16 IQE PIC (in SDH Mode)
SDH transport layer:
-cstm16- fpc/pic/port
SDH path layer:
-cau4-fpc/pic/port
[1:16]
NxDS0:
-ds- fpc/pic/port
[1-16]:[1-63]:[1-31]
404
Structure of Channelized IQ and Channelized IQE PICs
VT-mapped CT1:
VT-mapped T1:
-ct1-fpc/pic/port:
-t1-fpc/pic/port:
[1-48]:[1-28]
[1-48]:[1-28]
NxDS0:
-ds-fpc/pic/port:
[1-48]:[1-28]:[1-24]
OC12 and OC3 path layer :
OC12: -so-fpc/pic/port [1-4]
OC3: -so-fpc/pic/port [1-16]
Clear-channel T3:
-t3-fpc/pic/port:
[1-48]
HDLC
Clear-channel path
layer STM1 and
STM4:
-so-fpc/pic/port
HDLC