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10.3.5
Timer Control/Status Register (TCSR)
TCSR indicates the status flags and controls compare-match output.
TCSR_0
Bit
Bit Name
7
CMFB
6
CMFA
5
OVF
4
ADTE
3
OS3
2
OS2
1
OS1
0
OS0
Note:
*
Only 0 can be written, for flag clearing.
Rev. 1.00, 05/04, page 196 of 544
Initial
Value
R/W
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Compare-Match Flag B
[Setting condition]
When the values of TCNT_0 and TCORB_0 match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
Compare-Match Flag A
[Setting condition]
When the values of TCNT_0 and TCORA_0 match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
Timer Overflow Flag
[Setting condition]
When TCNT_0 overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
A/D Trigger Enable
Enables or disables A/D converter start requests by
compare-match A.
0: A/D converter start requests by compare-match A are
disabled
1: A/D converter start requests by compare-match A are
enabled
Output Select 3, 2
These bits specify how the TMO0 pin output level is to
be changed by compare-match B of TCORB_0 and
TCNT_0.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Output Select 1, 0
These bits specify how the TMO0 pin output level is to
be changed by compare-match A of TCORA_0 and
TCNT_0.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
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