Transmit Operation; Figure 14.4 Receive Timing - Renesas H8S/2111B Hardware Manual

KCLK
(pin state)
Start
KD
bit
(pin state)
KCLK
(input)
KCLK
(output)
KB7 to KB0 Previous data
PER
KBS
KBF
[1] [2] [3]
14.4.2

Transmit Operation

In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an
output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit,
and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit
processing flowchart is shown in figure 14.5, and the transmit timing in figure 14.6.
Rev. 1.00, 05/04, page 356 of 544
1 2 3
0 1
KB0 KB1

Figure 14.4 Receive Timing

Receive processing/
error handling
9 10 11
Parity bit Stop bit
7
Automatic I/O inhibit
Receive data
[4] [5]
Flag cleared
[6]