Operation; Host Interface Activation; Figure 15.2 Typical Lframe Timing; Figure 15.3 Abort Mechanism - Renesas H8S/2111B Hardware Manual

The timing of the LFRAME, LCLK, and LAD signals is shown in figures 15.2 and 15.3.
LCLK
LFRAME
LAD3–LAD0
Number of clocks
LCLK
LFRAME
LAD3–LAD0
15.4.3 A20 Gate
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086*-family CPU. A regular-speed A20 gate signal can be output under
firmware control. The fast A20 gate function that is speeded up by hardware is enabled by setting
the FGA20E bit to 1 in HICR0.
Note: An Intel microprocessor
Rev. 1.00, 05/04, page 398 of 544
Start ADDR
Cycle type,
direction,
and size
1 1

Figure 15.2 Typical LFRAME Timing

Start ADDR
Cycle type,
direction,
and size

Figure 15.3 Abort Mechanism

TAR Sync
4 2 1
TAR Sync
Slave must stop driving
Too many Syncs
cause timeout
Data TAR Start
2 2 1
Master will
drive high