Table 10.3 Clock Input To Tcnt And Count Condition (3) - Renesas H8S/2111B Hardware Manual

Table 10.3 Clock Input to TCNT and Count Condition (3)

Channel CKS2 CKS1
TMR_B 0 0
0 0
0 1
0 1
1 0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
TMR_A 0 0
0 0
0 1
0 1
1 0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Notes: * If the TMR_B clock input is set as the TCNT_A overflow signal and the TMR_A clock
input is set as the TCNT_B compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.
TCR
CKS0 CKSA
0 —
1 —
0 —
1 —
0 —
0 —
1 —
0 —
1 —
0 —
1 —
0 —
1 —
0 0
1 0
0 0
1 0
0 0
0 1
1 1
0 1
1 1
0 1
1 —
0 —
1 —
TCRAB
CKSB Description
0 Disables clock input
Increments at φ/4
0
Increments at φ/256
0
Increments at φ/2048
0
0 Disables clock input
1 Disables clock input
Increments at φ/4096
1
Increments at φ/8192
1
Increments at φ/16384
1
1 Increments at overflow signal from
TCNT_A*
— Increments at rising edge of external
clock
— Increments at falling edge of external
clock
— Increments at both rising and falling
edges of external clock
— Disables clock input
Increments at φ
—
Increments at φ/2
—
Increments at φ/4
—
— Disables clock input
— Disables clock input
Increments at φ/2048
—
Increments at φ/4096
—
Increments at φ/8192
—
— Increments at compare-match A from
TCNT_B*
— Increments at rising edge of external
clock
— Increments at falling edge of external
clock
— Increments at both rising and falling
edges of external clock
Rev. 1.00, 05/04, page 195 of 544