Mask Signal Generation Timing; Figure 9.15 Timing Of Input Capture Mask Signal Setting; Figure 9.16 Timing Of Input Capture Mask Signal Clearing - Renesas H8S/2111B Hardware Manual

Bit single-chip microcomputer h8s family / h8s/2100 series
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9.5.10

Mask Signal Generation Timing

When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a
signal that masks the ICRD input capture signal is generated. The mask signal is set by the input
capture signal. The mask signal is cleared by the sum of the ICRD contents and twice the
OCRDM contents, and an FRC compare-match. Figure 9.15 shows the timing of setting the mask
signal. Figure 9.16 shows the timing of clearing the mask signal.
φ
Input capture
signal
Input capture
mask signal

Figure 9.15 Timing of Input Capture Mask Signal Setting

φ
FRC
ICRD + OCRDM × 2
Compare-match
signal
Input capture
mask signal

Figure 9.16 Timing of Input Capture Mask Signal Clearing

Rev. 1.00, 05/04, page 176 of 544
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