Output Data Registers 1 To 3 (Odr1 To Odr3); Bidirectional Data Registers 0 To 15 (Twr0 To Twr15); Status Registers 1 To 3 (Str1 To Str3) - Renesas H8S/2111B Hardware Manual

• STR2
Bit Bit Name Initial Value Slave Host Description
7 DBU27 0
6 DBU26 0
5 DBU25 0
4 DBU24 0
3 C/D2 0
2 DBU22 0
1 IBF2 0
0 OBF2 0
Note: Only 0 can be written to clear the flag.
*
R/W
R/W R Defined by User
R/W R The user can use these bits as necessary.
R/W R
R/W R
R R Command/Data
When the host processor writes to an IDR register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
R/W R Defined by User
The user can use this bit as necessary.
R R Input Buffer Full
Set to 1 when the host processor writes to IDR. This
bit is an internal interrupt source to the slave
processor (this LSI). IBF is cleared to 0 when the
slave processor reads IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details
see table 15.3.
0: [Clearing condition]
When the slave processor reads IDR
1: [Setting condition]
When the host processor writes to IDR using I/O
write cycle
R/(W)* R Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. Cleared to 0 when the host processor reads
ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O
read cycle, or the slave processor writes 0 to the
OBF bit
1: [Setting condition]
When the slave processor writes to ODR
Rev. 1.00, 05/04, page 383 of 544